VLSI Implementation of High Resolution High Speed Low Latency Pipeline Floating point Adder/Subtractor for FFT Applications

This paper presents on-chip implementation of high speed low latency floating point adder /subtractor with high accuracy performance for FFT in OFDM transceiver. However due to high performance and high resolution, the floating point adder is matched with power network applications as well. The design was implemented for 32-bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating –point Arithmetic. The design is focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report indicating the latency of 4 clock cycles due to each stage operate within just one clock cycle. The unique structure of designed adder well thought out. The synthesis software provides results representing the estimated area and delay for design when it is pipelined to various depths.